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information in this document is provided in connection with intel products. intel assumes no liability whatsoever, including in fringement of any patent or copyright, for sale and use of intel products except as provided in intel?s terms and conditions of sale for such products. intel retains the right to make changes to these specifications at any time, without notice. microcontroller products may have minor varia- tions to this specification known as errata. copyright ? intel corporation, 2004 july 2004 order number: 273129-003 8xc251tb/tq high-performance chmos microcontroller commercial/express j real-time and programmed wait state bus operation j binary-code compatible with mcs 51 j pin compatible with 44-pin plcc and 40-pin pdip mcs 51 sockets j register-based mcs 251 architecture ? 40-byte register file ? registers accessible as bytes, words, or double words j enriched mcs 51 instruction set ? 16-bit and 32-bit arithmetic and logic instructions ? compare and conditional jump instructions ? expanded set of move instructions j linear addressing j 256-kbyte expanded external code/data memory space j rom options: 16 kbytes or without rom j 16-bit internal code fetch j 64-kbyte extended stack space j on-chip data ram options: 512-byte j 8-bit, 2-clock external code fetch in page mode j fast mcs 251 instruction pipeline j user-selectable configurations: ? external wait states (0-3 wait states) ? address range & memory mapping ? page mode ? extended data float timings or 8xc251sx compatible ac timings j 32 programmable i/o lines j eight maskable interrupt sources with four programmable priority levels j three flexible 16-bit timer/counters j hardware watchdog timer j programmable counter array ? high-speed output ? compare/capture operation ? pulse width modulator ? watchdog timer j two programmable serial i/o ports ? framing error detection ? automatic address recognition j high-performance chmos technology j static standby to 24-mhz operation j complete system development support ? compatible with existing tools ? mcs 251 tools available: compiler, assembler, debugger, ice j package options (pdip and plcc) ? ?
information in this document is provided in connection with in tel products. no license, expre ss or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. except as prov ided in intel's terms and conditions of sale for such products, intel assumes no liability whatsoever, and intel disclaims any express or implied warranty, relating to sale and/ or use of intel products including liability or warranties relating to fitness for a particular purpose, merchantability, or infr ingement of any patent, copyright or other in tellectual property righ t. intel products are not intended for use in medical, life saving , or life sustaining applications. intel may make changes to specifications and product descriptions at any time, without notice. contact your lo cal intel sales office or your distributor to obtain the lates t specifications and before placing your product order. designers must not rely on the absence or characteristics of a ny features or instructions mark ed "reserved" or "undefined." intel reserves these for futu re definition and shall have no responsibility whatsoever fo r conflicts or incompatibilities arising from future changes to them. the 8xc251tb/tq may contain design defects or errors known as errata which may cause the product to deviate from published specifications. current characterized errata are available on request. copies of documents which have an ordering number and are re ferenced in this document, or other intel literature, may be obtained from: intel corporation p.o. box 5937 denver co 80217-9808 or call 1-800-548-4725. many documents are available for download from intel?s we bsite at http://www.intel.com. copyright ? intel corporation 1997, 2003, 2004. *third party brands and names are the property of their respective owners.
revision history: date revision description november 1997 001 initial release of this document december 2003 002 removed references to 8xc251ta, 8xc251tp july 2004 003 to address the fact that many of the package prefix variables have changed, all package prefix variables in this document are now indicated with an "x".

1 8xc251tb/tq high-performance ch mos microcontroller commercial/express 1.0 introduction 1 2.0 nomenclature 2 3.0 pinout 4 4.0 signals 8 5.0 address map 11 6.0 electrical characteristics 12 6.1 d.c. characteristics 12 6.2 definition of ac symbols 14 6.3 a.c. characteristics 14 6.3.1 external bus cycles, nonpage mode 18 6.3.2 external bus cycles, page mode 21 6.3.3 definition of real-time wait symbols 24 6.3.4 external bus cycles, real-time wait states 24 6.4 ac characteristics ? seri al port, shift register mode 28 6.5 external clock drive 29 7.0 thermal characteristics 30
2 figures figure 1. 8 xc251tb/tq block diagram 1 figure 2. the 8 xc251tb/tq family nomenclature 2 figure 3. 8 xc251tb/tq 44-pin plcc package 4 figure 4. 8 xc251tb/tq 40-pin pdip packages 5 figure 5. external bus cycle: code fetch (nonpage mode) 18 figure 6. external bus cycle: data read (nonpage mode) 19 figure 7. external bus cycle: data write (nonpage mode) 20 figure 8. external bus cycle: code fetch (page mode) 21 figure 9. external bus cycle: data read (page mode) 22 figure 10. external bus cycle: data write (page mode) 23 figure 11. external bus cycle: code fetch/data read (nonpage mode) 24 figure 12. external bus cycle: data write (nonpage mode) 25 figure 13. external bus cycle: code fetch/data read (page mode) 26 figure 14. external bus cycle: data write (page mode) 27 figure 15. serial port waveform ? shift register mode 28 figure 16. external clock drive waveforms 29 figure 17. ac testing input, output waveforms 29 figure 18. float waveforms 30 tables table 1. description of product nomenclature 2 table 2. proliferation options 3 table 3. package information 3 table 4. 8 xc251tb/tq pin assignment 6 table 5. 8 xc251tb/tq plcc/dip pin assignments arranged by functional category 7 table 6. signal descriptions 8 table 7. memory signal selections (rd1:0) 10 table 8. 8 xc251tb/tq address map 11 table 9. dc characteristics at v cc = 4.5 ? 5.5 v 12 table 10. ac timing symbol definitions 14 table 11. ac characteristics 14 table 12. real-time wait ti ming symbol definitions 24 table 13. real-time wait ac timing 27 table 14. serial port timing ? shift register mode 28 table 15. external clock drive 29 table 16. thermal characteristics 30
1 8xc251tb/tq high-performan ce chmos microcontroller b2976-01 src2 (8) code address (24) clock & reset code bus (16) data ram 512 bytes or 1024 bytes code otprom/rom 8 kbytes or 16 kbytes watchdog timer timer/ counters pca two serial i/o ports peripherals port 2 drivers p2.7:0 port 0 drivers p0.7:0 port 3 drivers p3.7:0 port 1 drivers p1.7:0 data address (24) data bus (8) memory address (16) mcs ? 251 microcontroller core system bus and i/o ports i/o ports and peripheral signals src1 (8) ib bus (8) peripheral interface interrupt handler clock & reset bus interface instruction sequencer dst (16) alu data memory interface memory data (16) register file 1.0 introduction a member of the intel family of 8-bit mcs 251 micro - controllers, the 8xc251tb/tq is binary-code compatible with mcs 51 microcontrollers and pin compatible with 40-pin pdip and 44-pin plcc mcs 51 microcontrollers. mcs 251 microcontrollers feature an enriched instruction set, linear addressing, and efficient c-language support. the 8xc251tb/tq has 512 bytes or 1 kbyte of on-chip ram and is available with 8 kbytes or 16 kbytes of on-chip rom, or without rom. a variety of features can be selected by new user-programmable configu - rations. figure 1. 8xc251tb/tq block diagram
8xc251tb/tq high-performa nce chmos microcontroller 2 2.0 nomenclature program-memory options xxxxx xx x x 8 xx x packaging options temperature and burn-in options a2815-01 process information product family device speed figure 2. the 8xc251tb/tq family nomenclature table 1. description of product nomenclature parameter options description temperature and burn-in options no mark commercial operating temperature range (0c to 70c) with intel standard burn-in. x express operating temperature range (-40c to 85c) without intel standard burn-in. packaging options x 44-pin plastic leaded chip carrier (plcc) x 40-pin plastic dual in-line package (pdip) x 40-pin ceramic dual in-line package (ceramic dip) program memory options 0 without rom 3 rom process information c chmos product family 251 8-bit control architecture device memory options tb 1-kbyte ram/16-kbyte rom or without rom tq 512-byte ram/16-kbyte rom or without rom device speed 24 external clock frequency note: to address the fact that many of the package prefix va riables have changed, all package prefix variables in this document are now indicated with an "x".
8xc251tb/tq high-performan ce chmos microcontroller 3 ta b l e 2 lists the proliferation options. see figure 2 for the 8xc251tb/tq family nomenclature. table 2. proliferation options 8xc251tb/tq (0 ? 24 mhz; 5 v 10%) 80c251tb24 cpu-only 80c251tq24 cpu-only 83c251tb24 rom ta b l e lists the 8xc251tb/tq package definitions. table 3. package information pkg. definition temperature x 44 ld. plcc 0c to +70c x 40 ld. plastic dip 0c to +70c x 44 ld. plcc -40c to +85c note: to address the fact that many of the package prefix va riables have changed, all package prefix variables in this document are now indicated with an "x".
8xc251tb/tq high-performa nce chmos microcontroller 4 3.0 pinout b2977-01 ad4 / p0.4 ad5 / p0.5 ad6 / p0.6 ad7 / p0.7 ea# v ss2 ale psen# a15 / p2.7 a14 / p2.6 a13 / p2.5 p1.4 / cex1 p1.3 / cex0 / txd1 p1.2 / eci / rxd1 p1.1 / t2ex p1.0 / t2 v ss1 v cc ad0 / p0.0 ad1 / p0.1 ad2 / p0.2 ad3 / p0.3 p1.5 / cex2 p1.6 / cex3 / wait# p1.7 / cex4 / a17 / wclk rst p3.0 / rxd v cc2 p3.1 / txd p3.2 / int0# p3.3 / int1# p3.4 / t0 p3.5 / t1 39 38 37 36 35 34 33 32 31 30 29 8xc251tb 8xc251tq view of component as mounted on pc board 7 8 9 10 11 12 13 14 15 16 17 p3.6 / wr# p3.7 / rd# / a16 xtal2 xtal1 v ss v ss2 a8 / p2.0 a9 / p2.1 a10 / p2.2 a11 / p2.3 a12 / p2.4 18 19 20 21 22 23 24 25 26 27 28 6 5 4 3 2 1 44 43 42 41 40 figure 3. 8xc251tb/tq 44-pin plcc package
b2978-01 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 v cc ad0 / p0.0 ad1 / p0.1 ad2 / p0.2 ad3 / p0.3 ad4 / p0.4 ad5 / p0.5 ad6 / p0.6 ad7 / p0.7 ea# ale psen# a15 / p2.7 a14 / p2.6 a13 / p2.5 a12 / p2.4 a11 / p2.3 a10 / p2.2 a9 / p2.1 a8 / p2.0 p1.0 / t2 p1.1 / t2ex p1.2 / eci / rxd1 p1.3 / cex0 / txd1 p1.4 / cex1 p1.5 / cex2 p1.6 / cex3 / wait# p1.7 / cex4 / a17 / wclk rst p3.0 / rxd p3.1 / txd p3.2 / int0# p3.3 / int1# p3.4 / t0 p3.5 / t1 p3.6 / wr# p3.7 / rd# / a16 xtal2 xtal1 v ss 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 8xc251tb 8xc251tq view of component as mounted on pc board 8xc251tb/tq high-performan ce chmos microcontroller 5 figure 4. 8xc251tb/tq 40-pin pdip packages
table 4. 8xc251tb/tq pin assignment plcc dip name plcc dip name 1 v ss1 23 v ss2 2 1 p1.0/t2 24 21 a8/p2.0 3 2 p1.1/t2ex 25 22 a9/p2.1 4 3 p1.2/eci/rxd1 26 23 a10/p2.2 5 4 p1.3/cex0/txd1 27 24 a11/p2.3 6 5 p1.4/cex1 28 25 a12/p2.4 7 6 p1.5/cex2 29 26 a13/p2.5 8 7 p1.6/cex3/wait# 30 27 a14/p2.6 9 8 p1.7/cex4/a17/wclk 31 28 a15/p2.7 10 9 rst 32 29 psen# 11 10 p3.0/rxd 33 30 ale 12 v cc2 34 v ss2 13 11 p3.1/txd 35 31 ea# 14 12 p3.2/int0# 36 32 ad7/p0.7 15 13 p3.3/int1# 37 33 ad6/p0.6 16 14 p3.4/t0 38 34 ad5/p0.5 17 15 p3.5/t1 39 35 ad4/p0.4 18 16 p3.6/wr# 40 36 ad3/p0.3 19 17 p3.7/rd#/a16 41 37 ad2/p0.2 20 18 xtal2 42 38 ad1/p0.1 21 19 xtal1 43 39 ad0/p0.0 22 20 v ss 44 40 v cc 8xc251tb/tq high-performa nce chmos microcontroller 6
table 5. 8xc251tb/tq plcc/dip pin assignments arranged by functional category address & data input/output name plcc dip name plcc dip ad0/p0.0 43 39 p1.0/t2 2 1 ad1/p0.1 42 38 p1.1/t2ex 3 2 ad2/p0.2 41 37 p1.2/eci/rxd1 4 3 ad3/p0.3 40 36 p1.3/cex0/txd1 5 4 ad4/p0.4 39 35 p1.4/cex1 6 5 ad5/p0.5 38 34 p1.5/cex2 7 6 ad6/p0.6 37 33 p1.6/cex3/wait# 8 7 ad7/p0.7 36 32 p1.7/cex4/a17/wclk 9 8 a8/p2.0 24 21 p3.0/rxd 11 10 a9/p2.1 25 22 p3.1/txd 13 11 a10/p2.2 26 23 p3.4/t0 16 14 a11/p2.3 27 24 p3.5/t1 17 15 a12/p2.4 28 25 a13/p2.5 29 26 power & ground a14/p2.6 30 27 name plcc dip a15/p2.7 31 28 v cc 44 40 p3.7/rd#/a16 19 17 v cc2 12 p1.7/cex4/a17/wclk 9 8 v ss 22 20 v ss1 1 v ss2 23, 34 processor control ea# 35 31 name plcc dip p3.2/int0# 14 12 bus control & status p3.3/int1# 15 13 name plcc dip ea# 35 31 p3.6/wr# 18 16 rst 10 9 p3.7/rd#/a16 19 17 xtal1 21 18 ale 33 30 xtal2 20 19 psen# 32 29 8xc251tb/tq high-performan ce chmos microcontroller 7
8xc251tb/tq high-performa nce chmos microcontroller 8 4.0 signals table 6. signal descriptions (sheet 1 of 3) signal name type description alternate function a17 o 18th address bit (a17). output to memory as 18th external address bit (a17) in extended bus applications, depending on the values of bits rd0 and rd1 in configurati on byte uconfig0. see also rd# and psen#. p1.7/cex4/ wclk a16 o address line 16 . see rd#. rd# a15:8 1 o address lines . upper address lines for the external bus. p2.7:0 ad7:0 1 i/o address/data lines . multiplexed lower address lines and data lines for external memory. p0.7:0 ale o address latch enable . ale signals the start of an external bus cycle and indicates that valid address information is available on lines a15:8 and ad7:0. an external latc h can use ale to demultiplex the address from the address/data bus. cex4:0 i/o programmable counter array (pca) input/output pins . these are input signals for the pca capture mode and output signals for the pca compare mode and pca pwm mode. p1.6:4 p1.7/a17/ wait# p1.3/txd1 ea# i external access . directs program memory accesses to on-chip or off- chip code memory. for ea# = 0, all program memory accesses are off- chip. for ea# = 1, an access is to on-chip rom if the address is within the range of the on-chip rom; otherwise the access is off-chip. the value of ea# is latched at reset. for devic es without on-chip rom, ea# must be strapped to ground. eci i pca external clock input . external clock input to the 16-bit pca timer. p1.2/rxd1 int1:0# i external interrupts 0 and 1 . these inputs set bits ie1:0 in the tcon register. if bits it1:0 in the tcon register are set, bits ie1:0 are set by a falling edge on int1#/int0#. if bits int1:0 are clear, bits ie1:0 are set by a low level on int1:0#. p3.3:2 p0.7:0 i/o port 0 . this is an 8-bit, open-drai n, bidirectional i/o port. ad7:0 p1.0 p1.1 p1.2 p1.7:3 i/o port 1 . this is an 8-bit, bidirectional i/o port with internal pullups. t2 t2ex eci/rxd1 cex3:1 cex4/a17/ wait#/ wclk cex0/txd1 p2.7:0 i/o port 2 . this is an 8-bit, bidirectional i/o port with internal pullups. a15:8 p3.0 p3.1 p3.3:2 p3.5:4 p3.6 p3.7 i/o port 3 . this is an 8-bit, bidirectional i/o port with internal pullups. rxd txd int1:0# t1:0 wr# rd#/a16
8xc251tb/tq high-performan ce chmos microcontroller 9 psen# o program store enable . read signal output. this output is asserted for a memory address range that depends on bits rd0 and rd1 in configu - ration byte uconfig0 (see rd#). ? rd# o read or 17th address bit (a16). read signal output to external data memory or 17th external address bit (a16), depending on the values of bits rd0 and rd1 in configuration byte uconfig0. (see psen#). p3.7/a16 rst i reset . reset input to the chip. holding this pin high for 64 oscillator periods while the oscillator is running resets the device. the port pins are driven to their reset conditions when a voltage greater than v ih1 is applied, whether or not the oscillator is running. this pin has an internal pulldown resistor, which allows t he device to be reset by connecting a capacitor between this pin and v cc . asserting rst when the chip is in idle mode or powerdown mode returns the chip to normal operation. ? rxd i/o receive serial data . rxd sends and receives data in serial i/o mode 0 and receives data in serial i/o modes 1, 2, and 3. p3.0 rxd1 i/o receive serial data 1 . rxd1 sends and receives data in serial i/o mode 0 and receives data in serial i/o modes 1, 2, and 3 for the 2nd serial port. p1.2/eci t1:0 i timer 1:0 external clock inputs . when timer 1:0 operates as a counter, a falling edge on the t1:0 pin increments the count. p3.5:4 t2 i/o timer 2 clock input/output . for the timer 2 capture mode, this signal is the external clock input. for the clock-out mode, it is the timer 2 clock output. p1.0 t2ex i timer 2 external input . in timer 2 capture mode, a falling edge initiates a capture of the timer 2 registers. in auto-reload mode, a falling edge causes the timer 2 registers to be reloaded. in the up-down counter mode, this signal determines the count direction: 1 = up, 0 = down. p1.1 txd o transmit serial data . txd outputs the shift clock in serial i/o mode 0 and transmits serial data in serial i/o modes 1, 2, and 3. p3.1 txd1 o transmit serial data 1 . txd1 outputs the shift clock in serial i/o mode 0 and transmits serial data in serial i/o modes 1, 2, and 3 for the 2nd serial port. p1.3/cex0 v cc pwr supply voltage . connect this pin to the +5v supply voltage. ? v cc2 pwr secondary supply voltage 2. this supply voltage connection is provided to reduce power supply noise. connection of this pin to the +5v supply voltage is recommended. however, when using the 8xc251sb as a pin-for-pin replacement for the 8xc51fx, v ss 2 can be unconnected without loss of compatibility. (not available on dip) ? v ss gnd circuit ground . connect this pin to ground. ? v ss1 gnd secondary ground . this ground is provided to reduce ground bounce and improve power supply bypassing. c onnection of this pin to ground is recommended. however, when using the 8xc251tb/tq as a pin-for-pin replacement for the 8xc51bh, v ss1 can be unconnected without loss of compatibility. (not available on dip) ? table 6. signal descriptions (sheet 2 of 3) signal name type description alternate function
8xc251tb/tq high-performa nce chmos microcontroller 10 v ss2 gnd secondary ground 2 . this ground is provided to reduce ground bounce and improve power supply bypassing. c onnection of this pin to ground is recommended. however, when using the 8xc251tb/tq as a pin-for-pin replacement for the 8xc51fx, v ss2 can be unconnected without loss of compatibility. (not available on dip) ? wait# i real-time wait state input. the real-time wait# input is enabled by writing a logical ?1? to the wcon.0 (rtwe) bit at s:a7h. during bus cycles, the external memory syste m can signal ?system ready? to the microcontroller in real time by co ntrolling the wait# input signal on the port 1.6 input. p1.6/cex3 wclk o wait clock output. the real-time wclk output is driven at port 1.7 (wclk) by writing a logical ?1? to the wcon.1 (rtwce) bit at s:a7h. when enabled, the wclk output produ ces a square wave signal with a period of one-half the oscillator frequency. p1.7/cex4/ a17 wr# o write. write signal output to external memory. p3.6 xtal1 i input to the on-chip, inverting, oscillator amplifier . to use the internal oscillator, a crystal/resonator circuit is connected to this pin. if an external oscillator is used, its output is connected to this pin. xtal1 is the clock source for internal timing. ? xtal2 o output of the on-chip, inverting, oscillator amplifier . to use the internal oscillator, a crystal/resonator circuit is connected to this pin. if an external oscillator is used, leave xtal2 unconnected. ? note: the descriptions of a15:8/p2.7:0 and ad7:0/p0.7:0 are fo r the nonpage-mode chip configuration (compatible with 44-pin plcc and 40-pin dip mcs 51 microcontrollers). if the chip is configured for page-mode operation, port 0 carries the lower address bits (a7:0), and port 2 carries the upper address bits (a15:8) and the data (d7:0). table 7. memory signal selections (rd1:0) rd1:0 p1.7/cex/ a17/wclk p3.7/rd#/a16 psen# wr# features 0 0 a17 a16 asserted for all addresses asserted for writes to all memory locations 256-kbyte external memory 0 1 p1.7/cex4/ wclk a16 asserted for all addresses asserted for writes to all memory locations 128-kbyte external memory 1 0 p1.7/cex4/ wclk p3.7 only asserted for all addresses asserted for writes to all memory locations 64-kbyte external memory. one additional port pin. 1 1 p1.7/cex4/ wclk rd# asserted for addresses 7f:ffffh asserted for 80:0000h asserted only for writes to mcs 51 microcontroller data memory locations. 64-kbyte external memory. compatible with mcs 51 micro - controllers. table 6. signal descriptions (sheet 3 of 3) signal name type description alternate function
8xc251tb/tq high-performan ce chmos microcontroller 11 5.0 address map table 8. 8xc251tb/tq address map internal address) description notes ff:ffffh ff:4000h external memory except the top eight byt es (ff:fff8h?ff:ffffh) which are reserved for the configuration array. 1, 3, 10 ff:3fffh ff:0000h external memory or on-chip nonvolatile memory (8kbytes ff:0000h - ff:1fffh, 16kbytes ff:0000h - ff:3fffh). 3, 4, 5 fe:ffffh fe:0000h external memory 3 fd:ffffh 02:0000h reserved 6 01:ffffh 01:0000h external memory 3 00:ffffh 00:e000h external memory or with configuration bit em ap# = 0, addresses in this range access on- chip code memory in region ff: (16 kbyte devices only). 5, 7 00:dfffh 00:0420h external memory 7 00:041fh 00:0080h on-chip ram (512 bytes 00:0020h - 00:0 21fh, 1024 bytes 00:0020h - 00:041fh) 7 00:007fh 00:0020h on-chip ram 8 00:001fh 00:0000h storage for r0?r7 of register file 2, 9 notes: 1. 18 address lines are bonded out (a15:0, a16:0, or a17:0 selected during chip configuration). 2. the special function registers (sfrs) and the register file have separate internal address spaces. 3. data in this area is accessi ble by indirect addressing only. 4. devices reset into internal or external starting locations depending on the state of ea# and configuration byte information see ea#. 5. the 16-kbyte rom devices allow internal locations ff:2000h?ff:3 fffh to map into region 00:. in this case, if ea# = 1, a data read to 00:e000h?00:ffffh is redirected to internal rom (see bit 1 in uconfig0). this is not available for 8- kbyte rom devices. 6. this reserved area returns indeterminate values. 7. data is accessible by direct and indirect addressing. 8. data is accessible by direct, indirect, and bit addressing. 9. data is accessible by direct, indirect, and register addressing. 10. eight addresses at the top of all external memory maps ar e reserved for current and futu re device configuration byte information.
8xc251tb/tq high-performa nce chmos microcontroller 12 6.0 electrical characteristics absolute maximum ratings storage temperature .................................. -65c to +150c voltage: ea# pin with respect to v ss 0 v to +13.0 v voltage: any other pin with respect to v ss -0.5 v to +6.5 v i ol per i/o pin............................................................... 15 ma power dissipation ......................................................... 1.5 w operating conditions t a (ambient temperature under bias): commercial ................................................. 0c to +70c express........................................................... -40c to +85c v cc (digital supply voltage) ............................ 4.5 v to 5.5 v v ss 0 v note: maximum power dissipation is based on package heat-transfer limitations, not device power consumption. notice: this document contains information on products being sampled or in the initial production phase of development. verify with your local intel sales office that you have the latest datasheet before finalizing a design. warning : stressing the device beyond the ?absolute maximum ratings? may cause permanent damage. these are stress ratings only. operation beyond the ?operating conditions? is not recommended and extended exposure beyond the ?operating conditions? may affect device 6.1 d.c. characteristics parameter values apply to all dev ices unless otherwise indicated. ............. ... ................................................................................... table 9. dc characteristics at v cc = 4.5 ? 5.5 v (sheet 1 of 2) symbol parameter min typical max units test conditions v il input low voltage (except ea#) -0.5 0.2 v cc ? 0.1 v v il1 input low voltage (ea#) 0 0.2 v cc ? 0.3 v v ih input high voltage (except xtal1, rst) 0.2 v cc + 0.9 v cc + 0.5 v v ih1 input high voltage (xtal1, rst) 0.7 v cc v cc + 0.5 v v ol output low voltage (port 1, 2, 3) 0.3 0.45 1.0 v i ol = 100 a i ol = 1.6 ma i ol = 3.5 ma (note 1, note 2) v ol1 output low voltage (port 0, ale, psen#) 0.3 0.45 1.0 v i ol = 200 a i ol = 3.2 ma i ol = 7.0 ma (note 1, note 2) v oh output high voltage (port 1, 2, 3, ale, psen#) v cc ? 0.3 v cc ? 0.7 v cc ? 1.5 v i oh = -10 a i oh = -30 a i oh = -60 a (note 3)
8xc251tb/tq high-performan ce chmos microcontroller 13 v oh1 output high voltage (port 0 in external address) v cc ? 0.3 v cc ? 0.7 v cc ? 1.5 v i oh = -200 a i oh = -3.2 ma i oh = -7.0 ma v oh2 output high voltage (port 2 in external address during page mode) v cc ? 0.3 v cc ? 0.7 v cc ? 1.5 v i oh = -200 a i oh = -3.2 ma i oh = -7.0 ma i il logical 0 input current (port 1, 2, 3) -50 a v in = 0.45 v i li input leakage current (port 0) +/-10 a 0.45 < v in < v cc i tl logical 1-to-0 transition current (port 1, 2, 3) -650 a v in = 2.0 v r rst rst pulldown resistor 40 225 k : c io pin capacitance 10 (note 4) pf f osc = 24 mhz t a = 25 c i pd powerdown current 10 (note 4) 20 a i dl idle mode current 35 (note 4) 44 ma f osc = 24 mhz i cc operating current 70 (note 4) 83 ma f osc = 24 mhz notes: 1. under steady-state (non-transient) conditions, i ol must be externally limited as follows: ? maximum i ol per port pin:10 ma ? maximum i ol per 8-bit port: port 0 26 ma ports 1?3 15 ma ? maximum total i ol for all output pins 71 ma if i ol exceeds the test conditions, v ol may exceed the related specification. pi ns are not guaranteed to sink current greater than the listed test conditions. 2. capacitive load ing on ports 0 and 2 may cause spurious noise pulses above 0.4 v on the low- level outputs of ale and ports 1, 2, and 3. the noise is due to external bus capacita nce discharging into the port 0 and port 2 pins when these pins change from high to low. in applications where capacitive loading exceeds 100 pf, the noise pulses on these signals may exceed 0.8 v. it may be desirable to qualify ale or other signals with a schmitt trigger or cmos-level input logic. 3. capacitive loading on ports 0 and 2 causes the v oh on ale and psen# to drop below the specification when the address lines are stabilizing. typical values are obtained using v cc = 5.0, t a = 25c and are not guaranteed. table 9. dc characteristics at v cc = 4.5 ? 5.5 v (sheet 2 of 2) symbol parameter min typical max units test conditions
14 8xc251tb/tq high-performa nce chmos microcontroller 6.2 definition of ac symbols table 10. ac timing symbol definitions signals conditions a address h high d data in l low l ale v valid q data out x no longer valid r rd#/psen# z floating w wr# 6.3 a.c. characteristics test conditions: capacitive load on all pins = 50 pf. table 11 lists ac timing parameters for the with no wait states. external wait states can be added by extending psen#/rd#/wr# and/or by exte nding ale. in the table, notes 2 and 3 mark parameters affected by an ale wait state, and notes 4 and 5 mark parameters affected by a psen#/rd#/wr# wait state. figure 6 through figure 8 show the bus cycles with the timing parameters. table 11. ac characteristics (sheet 1 of 4) symbol parameter @ max f osc (1) f osc variable units min max min max f osc xtal1 frequency n/a n/a 0 24 mhz t osc 1/f osc @ 16mhz @ 24mhz n/a n/a 62.5 41.7 ns t lhll ale pulse width @ 16mhz @ 24mhz 55.5 34.7 (0.5+m) 2t osc -7 ns (3) t avll address valid to ale low @ 16mhz @ 24mhz 49.5 28.7 (0.5+m) 2t osc -13 ns (3) t llax address hold after ale low @ 16mhz @ 24mhz 10 10 10 ns (4) t llaxa address hold after ale low @ 16mhz @ 24mhz 20 20 20 ns (5) t rlrh rd# or psen# pulse width @ 16mhz @ 24mhz 115 73.4 (1+n) 2t osc -10 ns (3,4) t rlrha rd# or psen# pulse width @ 16mhz @ 24mhz 93 51.4 (1+n) 2t osc -32 ns (3,5) t wlwh wr# pulse width @ 16mhz @ 24mhz 115 73.4 (1+n) 2t osc -10 ns (3,4) t wlwha wr# pulse width @ 16mhz @ 24mhz 93 51.4 (1+n) 2t osc -32 ns (3,5)
8xc251tb/tq high-performan ce chmos microcontroller 15 t llrl ale low to rd# or psen# low @ 16mhz @ 24mhz 10 10 10 ns (4) t llrla ale low to rd# or psen# low @ 16mhz @ 24mhz 20 20 20 ns (5) t lhax ale high to address hold @ 16mhz @ 24mhz 98 56.4 (1+m) 2t osc -27 ns (3,4) t lhaxa ale high to address hold @ 16mhz @ 24mhz 77.5 56.7 (0.5+m) 2t osc +15 ns (3,5) t rldv rd# or psen# low to valid data/instruction in @ 16mhz @ 24mhz 95 53.4 (1+n) 2t osc -30 ns (3,4) t rldva rd# or psen# low to valid data/instruction in @ 16mhz @ 24mhz 75 33.4 (1+n) 2t osc -50 ns (3,5) t rhdx data/instruction hold after rd# or psen# high @ 16mhz @ 24mhz 0 0 0 ns t rlaz rd#/psen# low to address float @ 16mhz @ 24mhz 10 10 10 ns t rhdz1 instruction float after psen# or rd# high @ 16mhz @ 24mhz 10 10 10 ns (4) t rhdz1a instruction float after psen# or rd# high @ 16mhz @ 24mhz 57.5 36.7 t osc -5 ns (5) t rhdz2 data float after psen# or rd# high @ 16mhz @ 24mhz 135 93.4 2t osc +10 ns (4) t rhdz2a data float after psen# or rd# high @ 16mhz @ 24mhz 182.5 120.1 3t osc -5 ns (5) table 11. ac characteristics (sheet 2 of 4) symbol parameter @ max f osc (1) f osc variable units min max min max
8xc251tb/tq high-performa nce chmos microcontroller 16 t rhlh2 rd# or psen# high to ale high (data) @ 16mhz @ 24mhz 135 93.4 2t osc +10 ns (4) t rhlh2a rd# or psen# high to ale high (data) @ 16mhz @ 24mhz 180.5 118.1 3t osc -7 ns (5) t rhlh1 rd# or psen# high to ale high (instruction) @ 16mhz @ 24mhz 10 10 10 ns (4) t rhlh1a rd# or psen# high to ale high (instruction) @ 16mhz @ 24mhz 55.5 34.7 t osc -7 ns (5) t whlh wr# high to ale low @ 16mhz @ 24mhz 135 93.4 2t osc +10 ns (4) t whlha wr# high to ale low @ 16mhz @ 24mhz 180.5 118.1 3t osc -7 ns (5) t avdv1 address (mux?d) valid to valid data/ instruction in @ 16mhz @ 24mhz 190 106.8 (2+m+n) 2t osc -60 ns (3,4) t avdv1a address (mux?d) valid to valid data/ instruction in @ 16mhz @ 24mhz 159.5 97.1 (1.5+m+n) 2t osc -28 ns (3,4) t avdv2 address (demux?d) valid to valid data/instruction in @ 16mhz @ 24mhz 212 128.8 (2+m+n) 2t osc -38 ns (3) t avdv3 address (p0)valid to valid instruction in @ 16mhz @ 24mhz 65 23.4 (1+n) 2t osc -60 ns (3) t avrl address valid to rd# or psen# low @ 16mhz @ 24mhz 85 43.4 (1+m) 2t osc -40 ns (3,4) t avrla address valid to rd# or psen# low @ 16mhz @ 24mhz 72.5 51.7 (0.5+m) 2t osc +10 ns (3,5) table 11. ac characteristics (sheet 3 of 4) symbol parameter @ max f osc (1) f osc variable units min max min max
8xc251tb/tq high-performan ce chmos microcontroller 17 t avwl1 address (mux?d) valid to wr# low @ 16mhz @ 24mhz 85 43.4 (1+m) 2t osc -40 ns (3,4) t avwl1a address (mux?d) valid to wr# low @ 16mhz @ 24mhz 72.5 51.7 (0.5+m) 2t osc +10 ns (3,5) t avwl2 address (demux?d) valid to wr# low @ 16mhz @ 24mhz 108 66.4 (1+m) 2t osc -17 ns (3,4) t avwl2a address (demux?d) valid to wr# low @ 16mhz @ 24mhz 135 93.4 (1+m) 2t osc +10 ns (3,5) t whqx data hold after wr# high @ 16mhz @ 24mhz 49.5 28.7 t osc -13 ns t qvwh data valid to wr# high @ 16mhz @ 24mhz 110 68.4 (1+n) 2t osc -15 ns (3) t whax wr# high to address hold @ 16mhz @ 24mhz 112 70.4 2t osc -13 ns notes: 1. 24 mhz xtal frequency. 2. specifications for psen# are identical to those for rd#. 3. in the formula, m = number of wait states (0 or 1) for ale and n = number of wait states (0,1,2 or 3) for rd#/psen#/wr#. 4. device configured with the default data float timing for fast memory interface (edf# = 1). 5. device configured with extended data float timing for slow memory interface (edf# = 0). table 11. ac characteristics (sheet 4 of 4) symbol parameter @ max f osc (1) f osc variable units min max min max
8xc251tb/tq high-performa nce chmos microcontroller 18 6.3.1 external bus cycles, nonpage mode xtal1 ale t lhll ? a7:0 t rhdz1 rd#/psen# p0 p2/a16/a17 t rhdx t rhlh1 t rlrh ? t llrl ? t avll ? t rldv ? t avrl ? t avdv1 ? t avdv2 ? t osc a4211-03 t lhax ? instruction in ? the value of this parameter depends on wait states. see the table of ac characteristics. a15:8/a16/a17 d7:0 t rlaz t llax figure 5. external bus cycle: code fetch (nonpage mode)
8xc251tb/tq high-performan ce chmos microcontroller 19 xtal1 ale t lhll ? a7:0 d7:0 rd#/psen# p0 p2/a16/a17 t rhdx t rhlh2 t rlrh ? t llrl ? t avll ? t llax t rldv ? t avrl ? t avdv1 ? t avdv2 ? t osc a4210-03 t lhax ? data in ? the value of this parameter depends on wait states. see the table of ac characteristics. a15:8/a16/a17 t rhdz2 t rlaz figure 6. external bus cycle: data read (nonpage mode)
wr# p0 p2/a16/a17 t lhll ? t wlwh ? t whlh a4179-01 xtal1 ale t osc t whqx t qvwh t whqx t avwl1 ? t avwl2 ? t whax a7:0 d7:0 data out a15:8/a16/a17 ? the value of this parameter depends on wait states. see the table of ac characteristics. t llax t lhax ? t avll ? 8xc251tb/tq high-performa nce chmos microcontroller 20 figure 7. external bus cycle: data write (nonpage mode)
8xc251tb/tq high-performan ce chmos microcontroller 21 6.3.2 external bus cycles, page mode xtal1 ale t lhll ? a15:8 d7:0 t rhdz1 rd#/psen# p2 p0/a16/a17 t rhdx t llrl ? t avll ? t rldv ? t rlaz t avrl ? t avdv1 ? t avdv2 ? t osc a4213-02 t lhax ? instruction in a7:0/a16/a17 d7:0 instruction in a7:0/a16/a17 page miss ?? page hit ?? t avdv3 ? the value of this parameter depends on wait states. see the table of ac characteristics. ?? a page hit (i.e., a code fetch to the same 256-byte "page" as the previous code fetch) requires one state (2 t osc ); a page miss requires two states (4 t osc ). ??? during a sequence of page hits, psen# remains low until the end of the last page-hit cycle. t llax ??? figure 8. external bus cycle: code fetch (page mode)
xtal1 ale t lhll ? t rhdz2 rd#/psen# p2 p0/a16/a17 t rhdx t rhlh2 t rlrh ? t llrl ? t avll ? t rldv ? t rlaz t avrl ? t avdv1 ? t avdv2 ? t osc a4212-03 t lhax ? data in ? the value of this parameter depends on wait states. see the table of ac characteristics. a15:8 a7:0/a16/a17 d7:0 t llax 8xc251tb/tq high-performa nce chmos microcontroller 22 figure 9. external bus cycle: data read (page mode)
wr# p2 p0/a16/a17 t lhll ? t wlwh ? t whlh a4182-01 xtal1 ale t osc t whqx t qvwh t whqx t avwl1 ? t avwl2 ? t whax a15:8 d7:0 data out a7:0/a16/a17 ? the value of this parameter depends on wait states. see the table of ac characteristics. t avll ? t llax t lhax ? 8xc251tb/tq high-performan ce chmos microcontroller 23 figure 10. external bus cycle: data write (page mode)
8xc251tb/tq high-performa nce chmos microcontroller 24 a7:0 wclk ale rd#/psen# wait# p0 p2 a15:8 a5000-02 state 1 state 2 state 3 state 1 (next cycle) t clyx min t clyv a7:0 d7:0 stretched a15:8 stretched rd#/psen# stretched t clyx max t rlyv t rlyx max t rlyx min 6.3.3 definition of real-time wait symbols table 12. real-time wait timing symbol definitions signals conditions a address l low d data x hold c wclk v setup y wait# w wr# r rd#/psen# 6.3.4 external bus cycles, real-time wait states figure 11. external bus cycle: code fetch/data read (nonpage mode)
a7:0 wclk ale wr# t wlyv wait# p0 p2 a5002-02 state 1 state 2 state 3 state 4 t clyx min t clyv d7:0 stretched a15:8 stretched wr# stretched t wlyx max t wlyx min t clyx max 8xc251tb/tq high-performan ce chmos microcontroller 25 figure 12. external bus cycle: data write (nonpage mode)
a15:8 wclk ale rd#/psen# wait# p2 p0 a7:0 a5001-02 state 1 state 2 state 3 state 1 (next cycle) t clyx min t clyv a15:8 d7:0 stretched a7:0 stretched rd#/psen# stretched t clyx max t rlyv t rlyx max t rlyx min 8xc251tb/tq high-performa nce chmos microcontroller 26 figure 13. external bus cycle: code fetch/data read (page mode)
a15:8 wclk ale wr# t wlyv wait# p2 p0 a5003-02 state 1 state 2 state 3 state 4 t clyx min t clyv d7:0 stretched a7:0 stretched wr# stretched t wlyx max t wlyx min t clyx max 8xc251tb/tq high-performan ce chmos microcontroller 27 figure 14. external bus cycle: data write (page mode) table 13. real-time wait ac timing symbol parameter min max units t clyv wait clock low to wait set-up 0 t osc ? 13 ns t clyx wait hold after wait clock low (2w)t osc + 5 (1+2w)t osc ? 20 ns (1) t rlyv psen#/rd# low to wait set-up 0 t osc ? 13 ns t rlyva psen#/rd# low to wait set-up 0 t osc ? 35 ns (2) t rlyx wait hold after psen#/rd# low (2w)t osc + 5 (1+2w)t osc ? 20 ns (1) t wlyv wr# low to wait set-up 0 t osc ? 13 ns t wlyva wr# low to wait set-up 0 t osc ? 35 ns (2) t wlyx wait hold after wr# low (2w)t osc + 5 (1+2w)t osc ? 20 ns (1) notes: 1. w = 0, 1, 2 ? is the number of real time wait states. 2. device configured with the extended data float timing.
8xc251tb/tq high-performa nce chmos microcontroller 28 6.4 ac characteristics ? serial port table 14. serial port timing ? shift register mode symbol parameter min max units t xlxl serial port clock cycle time 12t osc ns t qvsh output data setup to clock rising edge 10t osc ? 133 ns t xhqx output data hold after clock rising edge 2t osc ? 117 ns t xhdx input data hold after clock rising edge 0 ns t xhdv clock rising edge to input data valid 10t osc ? 133 ns , shift register mode valid valid valid valid valid valid valid valid rxd (in) rxd (out) txd 01 2 3 4 5 6 7 t qvxh t xlxl t xhdx t xhqx t xhdv a2592-02 set ti ? set ri ? t av ? ? ti and ri are set during s1p1 of the peripheral cycle following the shift of the eighth bit. figure 15. serial port waveform ? shift register mode
8xc251tb/tq high-performan ce chmos microcontroller 29 6.5 external clock drive table 15. external clock drive symbol parameter min max units 1/t clcl oscillator frequency (f osc ) 24 mhz t chcx high time 20 ns t clcx low time 20 ns t clch rise time 10 ns t chcl fall time 10 ns 0.7 v cc a4119-01 0.45 v v cc ? 0.5 0.2 v cc ? 0.1 t chcl t clcx t clcl t clch t chcx figure 16. external clock drive waveforms ac inputs during testing are driven at v cc ? 0.5v for a logic 1 and 0.45 v for a logic 0. timing measurements are made at 0.45 v inputs outputs a4118-01 v ih min v ol max v cc ? 0.5 0.2 v cc + 0.9 0.2 v cc ? 0.1 a min of v ih for a logic 1 and v ol for a logic 0. figure 17. ac testing input, output waveforms
v load + 0.1 v v load ? 0.1 v timing reference points v load v oh ? 0.1 v v ol + 0.1 v for timing purposes, a port pin is no longer floating when a 100 mv change from load voltage occurs and begins to float when a 100 mv change from the loading v oh /v ol level occurs with i ol / i oh = 20 ma. a4117-01 8xc251tb/tq high-performa nce chmos microcontroller 30 figure 18. float waveforms 7.0 thermal characteristics all thermal impedance data is approximate for static air conditions at 1 watt of power dissipation. values change depending on operating conditions and application requirements. the intel packaging handbook (order number 240800) describes intel?s thermal impedance test methodology. table 16. thermal characteristics package type 44-pin plcc 46c/w 16c/w 40-pin pdip 45c/w 16c/w ja jc

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